--===========================================================================--
-- Naziv		: Instruction decode
-- Ime fajla	: id.vhdl  
-- Verzija		: 0.1
--===========================================================================-- 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity id is 
	  port (
	    --IN
			reset,clk : in std_logic;  
			flush,stall : in std_logic;         
			PC_if     : in std_logic_vector (15 downto 0 );  --PC iz fetch faze
			I_DBUS   : in std_logic_vector(15 downto 0);           -- Instrukcija na data magistrali iz IMem
		--OUT	
			PC_id    : out std_logic_vector (15 downto 0 ); --PC iz fetch faze; PC se mora prosledjivati
			R1_id,R2_id,R3_id     : out std_logic_vector (3 downto 0 );
			Imm_id         : out std_logic_vector (7 downto 0 );
			opcode_id          :out std_logic_vector(4 downto 0)
	
			
			
	  );
end;
architecture id_AR of id is
signal IR       :  std_logic_vector(15 downto 0);
begin
	id_PR: process (clk,reset,flush) is
	begin
		if (reset='1' or flush='1') then
			PC_id <= "0000000000000000";
			IR <= "0000000000000000";
		--elsif falling_edge (clk) then
		elsif rising_edge (clk) then
			if stall='0' then 
				--??? Zasto -1? ne treba -1
				PC_id <= std_logic_vector(unsigned(PC_if)); -- uzima se na silaznu ivicu, a u IF fazi ce se vec promeniti PC
				IR <= I_DBUS;
			end if;
		end if;
	end process;
	
	R1_id <= IR(3 downto 0); 
	R2_id <= IR(7 downto 4); 
	R3_id <= IR(11 downto 8); 
	Imm_id <= IR(11 downto 4); 
	opcode_id <= "00000" when IR="0000000000000000" else
				 "00000" when IR="ZZZZZZZZZZZZZZZZ" else
				 '1'&IR(11 downto 8) when (IR(15 downto 12) = "0000") else --Mozda mora"1" umesto '1'
				 '0'&IR(15 downto 12);
				 
end id_AR;